ASIC Design Verification Engineer Seen this week

The Role

You will verify the functionality, performance, and robustness of custom silicon designs for K2's satellites. This is a hands-on role with high ownership and deep technical engagement. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.

Responsibilities

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
• Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
• Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
• Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
• Participate in design reviews and microarchitecture discussions.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
• Proficiency with a simulation tool (VCS, Xcelium, Questa), waveform debug tool (Verdi, SimVision), and coverage tool.
• Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
• Familiarity with a scripting language (Python, Perl, TCL) and revision control system (Git).

Nice to Have

• Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
• Familiarity with developing and integrating reference models.
• Understanding of RTL design flows and industry standard interfaces (APB/AHB/AXI).
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems.

Compensation and Benefits

• Base salary range: $130,000 to $200,000 plus equity.
• Salary based on knowledge, skills, education, and experience level.
• Comprehensive benefits include paid time off, medical/dental/vision coverage, life insurance, and paid parental leave.