Senior ASIC Emulation Engineer Verified today

K2 Space · Seattle, WA · Electronics · first seen 2026-08-04

The Role

Lead the bring-up, deployment, and optimization of pre-silicon emulation platforms for K2's high-power satellite ASICs. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable hardware/software co-development and accelerate verification cycles. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon and system methodology.

Responsibilities

Build, integrate, and maintain full-chip, multi-chip, and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce.
Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity, and stability.
Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
Support system-level testing by enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end-to-end workloads.
Accelerate verification throughput by helping the DV team run targeted and high-value tests in emulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
Enable firmware, bootloader, driver, and software teams by providing robust emulation platforms and assisting in HW/SW integration debug.
Run emulation workloads, triage failures, perform root-cause analysis, and collaborate across design and verification to resolve issues.
Maintain and enhance automation for compile flows, regression management, and continuous integration.
Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulation best practices.
Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation.
Manage interactions with external IP providers or emulation partners when needed.

Qualifications

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in ASIC/SoC development, focused on emulation.
Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
Hands-on expertise with major emulation platforms (Palladium, ZeBu, Veloce), including model build, debug, and performance optimization.
Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++-based system-level testing.
Familiarity with industry-standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.
Experience driving cross-functional debug involving RTL, DV, firmware, physical design, and validation teams.
Understanding of pre- and post-silicon debug methodologies and correlation workflows.

Nice to Have

Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards).
Experience with low-power modes and power-aware emulation.
Experience with analog/mixed-signal behavioral models in emulation environments.
Experience with SERDES and high-speed data protocols such as PCIe, Ethernet, USB, or multi-gigabit PHYs.

Compensation and Benefits

Base salary range: $170,000 to $250,000, plus equity in the company.
Salary based on knowledge, skills, education, and experience level.
Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, and paid parental leave.

Export Compliance

This role requires access to information and items controlled by U.S. export control regulations under the International Traffic in Arms Regulation (ITAR). You must be a U.S. Person as defined by 22 C.F.R. section 120.15 (U.S. citizen, lawful permanent resident, or certain protected individuals) or otherwise eligible for a federally issued export control license.