RFIC Layout Designer (RFIC Engineering) Verified today
About this role
SpaceX is developing Starlink, the world's largest satellite constellation delivering fast, reliable broadband internet globally. We design, build, test and operate all parts of the system: thousands of satellites, consumer receivers, and software. You will join the IC design team working on multiple silicon projects driving more integration, lower power, and mixed-signal architectures for deployment in space and ground infrastructure.
You will be the layout lead on a cross-disciplinary team with systems architects, ASIC designers, firmware engineers, verification engineers, and manufacturing specialists. You will own the technical discipline of layout and work closely with RFIC and mixed-signal designers on full-chip custom analog and RF designs.
Your responsibilities
- Work with IC designers and chip leads to determine chip floor plan, including power and ground distribution strategies and pad locations with packaging engineers
- Estimate layout schedules and identify areas of complexity for early investigation
- Perform layout of custom RF and analog circuit blocks, optimizing for matching and minimizing parasitic capacitance
- Execute design rule checking, electrical rule checking, and layout versus schematic verification; resolve errors
- Integrate top-level layout with electrostatic discharge structures and pad assembly; perform final tape out including density fill, design for manufacturability checks, and GDS delivery to foundry
- Work with EDA suppliers to trial new tools and features
- Generate layout guides and demos to share improvements with the team
Basic qualifications
- Bachelor's degree in electrical or computer engineering plus 1+ years of professional IC layout design experience; OR 3+ years of professional integrated circuit layout design experience in lieu of a degree
Preferred skills and experience
- Strong analog layout skills
- Advanced node IC layout experience (22nm, 16nm, 7nm, 5nm or below)
- Layout of high-frequency circuits up to 50GHz
- Layout of sensitive RF blocks: low noise amplifiers, voltage controlled oscillators, mixers
- Skill programming
- Shell scripting, Perl, Python or similar languages
- Revision control systems management
- Circuit design experience
- Understanding of layout for device matching, coupling and noise isolation
- Linux working knowledge
- Excellent oral and written communication
- Ability to work independently on challenging problems
Additional requirements
- Must be willing to work extended hours and weekends to meet critical milestones
Compensation and benefits
Pay range: Level 1 $105,000 - $145,000 / Level 2 $120,000 - $175,000. Actual level and salary determined case-by-case based on job-related knowledge, skills, education and experience.
Total rewards include: long-term stock or cash awards, discretionary bonuses, employee stock purchase plan, comprehensive medical/vision/dental coverage, 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, 3 weeks paid vacation, 10+ paid holidays annually. Washington State employees accrue paid sick time per state and federal law. Company shuttles offered from select Seattle locations to Redmond office Monday to Friday.
ITAR requirement
To conform to U.S. Government export regulations, applicant must be a U.S. citizen or national, U.S. lawful permanent resident (green card holder), Refugee under 8 U.S.C. 1157, or Asylee under 8 U.S.C. 1158, or be eligible to obtain required authorizations from the U.S. Department of State.