Sr. RFIC Layout Designer (RFIC Engineering) Verified today
About the role
SpaceX is deploying Starlink, the world's largest satellite constellation delivering fast, reliable broadband to millions globally. You will join the IC design team working on silicon projects that advance integration, reduce power consumption, and enable mixed-signal architectures for space and ground systems.
As Senior RFIC Layout Designer, you will lead layout discipline at the technical level, partnering with RFIC and mixed-signal designers on full-chip layout of custom analog and RF designs. You will work alongside cross-functional teams spanning systems architecture, ASIC design, firmware, verification, validation, product engineering, and manufacturing.
What you will do
- Work with IC designers and chip leads to determine chip floor plan, including power and ground distribution strategies and pad placement with packaging engineers
- Estimate layout schedules accurately and identify areas of early investigation
- Perform layout of custom RF and analog circuit blocks, focusing on matching and parasitic capacitance minimization
- Execute design rule checking, electrical rule checking, and layout versus schematic verification; resolve errors
- Perform top-level layout integration with ESD structures, pad assembly, and final tape-out (density fill, design for manufacturability checks, GDS delivery to foundry)
- Collaborate with EDA suppliers on new tools and features
- Create guides and demonstrations to showcase layout technique improvements across the team
What we need
Required:
- Bachelor's degree in electrical or computer engineering plus 5+ years of professional IC layout design experience, OR 8+ years of IC layout design experience without degree
Preferred:
- Strong analog layout skills
- Experience with advanced-node layouts (22nm, 16nm, 7nm, 5nm or below)
- Layout experience at frequencies up to 50GHz
- Experience laying out sensitive RF blocks (low noise amplifiers, voltage controlled oscillators, mixers)
- Skill programming experience
- Shell scripting, Perl, Python or similar languages
- Revision control system management
- Circuit design experience
- Understanding of layout for device matching, coupling, and noise isolation
- Linux working knowledge
- Excellent oral and written communication
- Ability to work independently on challenging problems
Working conditions
Must be willing to work extended hours and weekends as needed to meet critical milestones.
Compensation
Level 3: $140,000-$235,000 base salary, determined by job-related knowledge and skills, education, and experience.
Additional benefits include long-term stock or cash awards, discretionary bonuses, employee stock purchase plan, comprehensive medical/vision/dental coverage, 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, 3 weeks paid vacation, 10+ paid holidays annually, and company shuttles from Seattle locations to Redmond office Monday to Friday. Employees in Washington State accrue paid sick time per state and federal law.
ITAR requirement
To comply with U.S. Government export regulations, you must be a U.S. citizen or national, U.S. lawful permanent resident, Refugee under 8 U.S.C. § 1157, or Asylee under 8 U.S.C. § 1158, or be eligible to obtain required authorization from the U.S. Department of State.